Design a divider for unsigned binary numbers that will divide a 8-bit dividend by a 3-bit divisor to give a 5-bit quotient. Assume that the start signal (St) is 1 for exactly one clock time. When St = 1, the dividend register should be loaded from the input bus. On the next clock cycle, the divisor register should be loaded from the same input bus. Then, if the quotient would require more than 5 bits, an overflow would occur, so V should be set to 1, and the controller should go back to the reset state. Otherwise, the controller should generate the appropriate sequence of shift and subtract signals and turn on a done signal when division is complete. Use an 9-bit dividend register and store the quotient in the lower 3 bits of the register.
1) Draw a block diagram of the system showing registers, adders, MUXes, and other components. Define the necessary signals. specify the size of registers, adders, etc. Provide an active-high asynchronous RESET for your design.
2) Draw a state graph for the CONTROL CIRCUIT.
3) Based on the results of steps 1 and 2, write a VHDL description of the system using control signals and TWO PROCESSES as in figure 20-7 ( page 657 of text book).
• First process : generates the next-state an control signals
• Second process : updates the states and other registers (This is your clock dependent process)
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