ECEN 2350 Digital Logic Fall 2013 9-28-13 P. Mathys 1) (a) Implement a 4-bit ripple carry adder in Verilog using the circuit structure shown in Figure 3.14 in the book. Use a structural description of the circuit using AND, OR, and XOR gates with delay D for AND and OR gates and delay 2*D for XOR gates, where the delay parameter can be set, e.g., as D=0 for functional simulations, or as D=5 for timing simulations. An example of how to use and test gates with delays is shown in the Appendix. Use the following header for the RippleCarryAdder module: 1
Note that S, X, Y are defined as vectors. The individual bits are obtained from the vectors as S[3] (most significant bit), S[2], S[1], S[0] (least significant bit), and similarly for X and Y. Bring a printout of your Verilog code to class for grading. (b) Write a testbench for a functional simulation of the ripple carry adder. Set D=0 for this simulation. Bring a printout of the waveforms you generated to class for grading. (c) Write a testbench for a timing simulation that identifies the maximum delays from Cin to Cout and from each input, either X[i] or Y[i], to Cout. Set D=5 for this simulation. Bring a printout of the waveforms you generated to class for grading. 2
Appendix: Example of Verilog Code with Gate Delays The Verilog module below implements the function f(x1, x2, x3) = m(3, 6) =) f = x2 (x1 x3) using a delay D = 5 for the AND gate and a delay 2 D = 10 for the XOR gate. To test for the delays from each xi to the output f, a sequence of specific test vectors is created in the initial block (the #20 statements specify a delay of 20 time units before the command is executed). For example, the sequence of test vectors 3’b010, 3’b011, 3’b010 tests the delay from x3 to output f. The resulting timing diagram, showing a delay of 15 ns from x1 to f, and a delay of 5 ns from x2 to f is shown next. 3
c 2012–2013, P. Mathys. Last revised: 9-28-13, PM. 4