1.Design a pipeline ALU that can add two 8-bit integers. Assume that each stage can add two 2 -bit integers and employ sufficient number of stages. Show the operation of the pipeline using an RT.
2.Assume that the CPU uses four cycles(fetch, calculate address, memory read, move the data to the designation register) for a load store instruction; correspondingly four cycles for a STORE instruction and three cycles(Fetch, Computer results, move them to the designation register) for other register to register instructions.
1.Design a pipeline ALU that can add two 8-bit integers. Assume that each stage can add two 2 -bit integers and employ sufficient number of stages. Show the operation of the pipeline using an RT.
2.Assume that the CPU uses four cycles(fetch, calculate address, memory read, move the data to the designation register) for a load store instruction; correspondingly four cycles for a STORE instruction and three cycles(Fetch, Computer results, move them to the designation register) for other register to register instructions. Show the reservation pattern for the following program:
LOAD Z Acc
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